Document revision date: 30 March 2001

## OpenVMS Calling Standard

Previous | Contents | Index

### 3.4.7 Procedure Descriptor for Null Frame Procedures

The null frame procedure descriptor built by a compiler provides information about a procedure with no frame. The size of the descriptor is 16 bytes (defined by PDSC$K_NULL_SIZE).

The fields defined in the null frame descriptor are illustrated in Figure 3_7 and described in Table 3-5.

Figure 3-7 Null Frame Procedure Descriptor (PDSC) Format

Table 3-5 Contents of Null Frame Procedure Descriptor (PDSC)
Field Name | Contents
--- | ---
PDSC$W_FLAGS | The PDSC descriptor flag bits <15:0> are defined as follows:
PDSC$V_KIND | A 4-bit field <3:0> that identifies the type of procedure descriptor. For a null frame procedure, this field must specify a value 8 (defined by constant PDSC$K_KIND_NULL).
Bits 4--7 | Must be 0.
PDSC$V_REI_RETURN | Bit 8. If set to 1, the procedure expects the stack at entry to be set, so an REI instruction correctly returns from the procedure. Also, if set, the contents of the PDSC$B_SAVE_RA field are unpredictable and the return address is found on the stack.
Bit 9 | Must be 0 (reserved).
PDSC$V_BASE_FRAME | For compiled code, this bit must be 0. If set to 1, indicates the logical base frame of a stack that precedes all frames corresponding to user code. The interpretation and use of this frame and whether there are any predecessor frames is system software defined (and subject to change).
Bit 11 | Must be 0 (reserved).
PDSC$V_NATIVE | For compiled code, this bit must be set to 1.
PDSC$V_NO_JACKET | For compiled code, this bit must be set to 1.
PDSC$V_TIE_FRAME | For compiled code, this bit must be 0. Reserved for use by system software.
Bit 15 | Must be 0 (reserved).
PDSC$V_FUNC_RETURN | A 4-bit field <11:8> that describes which registers are used for the function value return (if there is one) and what format is used for those registers. Table 3-7 lists and describes the possible encoded values of PDSC$V_FUNC_RETURN.
PDSC$W_SIGNATURE_OFFSET | A 16-bit signed byte offset from the start of the procedure descriptor. This offset designates the start of the procedure signature block (if any). A 0 in this field indicates that no signature information is present. Note that in a bound procedure descriptor (as described in Section 3.7.4), signature information might be present in the related procedure descriptor. A 1 in this field indicates a standard default signature. An offset value of 1 is not otherwise a valid offset because both procedure descriptors and signature blocks must be quadword aligned.
PDSC$Q_ENTRY | The absolute address of the first instruction of the entry code sequence for the procedure.

## 3.5 Procedure Signatures

As a way to enhance certain aspects of program interoperation between images built from native Alpha code and images translated from VAX code, native Alpha compilers can optionally generate information that describes the parameters of a procedure. This auxiliary information is called procedure signature information, or sometimes just signature information.

Signature information is used when a call from a native procedure passes control to a translated procedure and vice versa. Translated VAX code on Alpha processors uses a VAX argument list and function return conventions as described in Sections 2.4 and 2.5. Here, the signature information is used to control how passed and returned arguments according to Alpha conventions are manipulated and placed for use by translated VAX code and vice versa.

If a procedure is compiled with signature information, PDSC$W_SIGNATURE_OFFSET contains a byte offset from the procedure descriptor to the start of a procedure signature control block. The maximum size of the procedure signature control block is 72 bytes (defined by constant PSIG$K_MAX_SIZE). The fields defined in the procedure signature information block are illustrated in Figure 3_8 and described in Table 3-6.

Figure 3-8 Procedure Signature Information Block (PSIG)

Table 3-6 Contents of the Procedure Signature Information Block (PSIG)
Field Name | Contents
--- | ---
PSIG$V_FUNC_RETURN | A 4-bit field <3:0> that describes which registers are used for the function value return (if there is one) and what format is used for those registers. Table 3-7 lists and describes the possible encoded values of PSIG$V_FUNC_RETURN.
PSIG$V_REG_ARG_INFO | A 24-bit field <27:4> that is divided into six groups of 4 bits that correspond to the six arguments that can be passed in registers. These groups describe how each of the first six arguments are to be passed in registers of the first group (bits <7:4>) describing the first argument. Each register argument signature group is encoded as follows:
Value | Name | Meaning1,2
--- | --- | ---
0 | RASE$K_RA_NOARG | Argument is not present
1 | RASE$K_RA_Q | 64-bit argument passed in an integer register
2 | RASE$K_RA_I32 | 32-bit argument sign extended to 64 bits passed in an integer register
3 | RASE$K_RA_U32 | 32-bit unsigned argument zero extended to 64 bits passed in an integer register
4 | RASE$K_RA_FF | F_floating argument passed in a floating-point register
5 | RASE$K_RA_FD | D_floating argument passed in a floating-point register
6 | RASE$K_RA_FG | G_floating argument passed in a floating-point register
7 | RASE$K_RA_FS | S_floating argument passed in a floating-point register
8 | RASE$K_RA_FT | T_floating argument passed in a floating-point register
9--15 |  | Reserved for future use
PSIG$V_SUMMARY | A 4-bit field <31:28> that contains coded argument signature information as follows:
Bit | Name | Meaning
--- | --- | ---
0, 1 | PSIG$M_SU_ASM | Summary of arguments 7 through PSIG$B_ARG_COUNT: 00 = All arguments are 64-bit or not used 01 = All arguments are 32-bit sign extended or not used 10 = Reserved 11 = Other (not 00 or 01)
2 | PSIG$M_SU_VLIST | VAX formatted argument list expected
3 |  | Must be 0 (reserved)
PSIG$M_SU_ASM values of 00 and 01 (binary) allow a quick test for the occurrence of either an all 32-bit or an all 64-bit argument list. The values for the PSIG$V_MEMORY_ARG_INFO field must be valid even when these occurrences apply.
PSIG$B_ARG_COUNT | Unsigned byte (bits 0--7) that specifies the number of 64-bit argument items described in the argument signature information. This count includes the first six arguments.
PSIG$V_MEMORY_ARG_INFO | Array of 2-bit values that describe each of arguments 7 through PSIG$B_ARG_COUNT. PSIG$S_MEMORY_ARG_INFO data is only defined for the arguments described by PSIG$B_ARG_COUNT. These memory argument signature bits are defined as follows:
Value | Name | Meaning1
--- | --- | ---
0 | MASE$K_MA_Q | 64-bit argument
1 |  | Reserved
2 | MASE$K_MA_I32 | 32-bit sign-extended argument
3 |  | Reserved

1For more specific impact on the converted field value, see Section 3.5.1.
2The X_floating and X_floating complex data types do not appear in this table because these types are not passed using the by value mechanism (see Section 3.8.5.1).

Table 3-7 Function Return Signature Encodings
Value | Name | Meaning1,2
--- | --- | ---
0 | PSIG$K_FR_I64 | 64-bit result in R0 or No function result provided or First parameter mechanism used
1 | PSIG$K_FR_D64 | 64-bit result with low 32 bits sign extended in R0 and high 32 bits sign extended in R1
2 | PSIG$K_FR_I32 | 32-bit sign extended to 64-bit result in R0
3 | PSIG$K_FR_U32 | 32-bit unsigned result (zero extended) in R0
4 | PSIG$K_FR_FF | F_floating result in F0
5 | PSIG$K_FR_FD | D_floating result in F0
6 | PSIG$K_FR_FG | G_floating result in F0
7 | PSIG$K_FR_FS | S_floating result in F0
8 | PSIG$K_FR_FT | T_floating result in F0
9, 10 |  | Reserved for future use
11 | PSIG$K_FR_FFC | F_floating complex result in F0 and F1
12 | PSIG$K_FR_FDC | D_floating complex result in F0 and F1
13 | PSIG$K_FR_FGC | G_floating complex result in F0 and F1
14 | PSIG$K_FR_FSC | S_floating complex result in F0 and F1
15 | PSIG$K_FR_FTC | T_floating complex result in F0 and F1

1For more specific impact on the converted field value, see Section 3.5.1.
2The X_floating and X_floating complex data types do not appear in this table because these types are not passed using the by value mechanism (see Section 3.8.5.1).

### 3.5.1 Call Parameter PSIG Conversions

Where a VAX image is translated to an Alpha image, the VAX registers R0--15 are represented using the lower half of the corresponding Alpha registers R0--15 at call interface boundaries. No "type conversion" is performed in making parameters from either native or translated code available to each other. However, it is important to understand the effects of the PSIG field values when interfacing between native and translated environments.

Note that an address under OpenVMS Alpha is described using RASE$K_RA_I32 or MASE$K_MA_I32 as appropriate.

#### 3.5.1.1 Native-to-Translated Code PSIG Conversions

The specific impact of the native-to-translated call conversions of the PSIG$V_REG_ARG_INFO and the PSIG$V_FUNC_RETURN field values are listed in Table 3-8.

Table 3-8 Native-to-Translated Conversion of the PSIG Field Values
Name | Impact
--- | ---
PSIG$V_REG_ARG_INFO Field Conversions
RASE$K_RA_Q | The low-order 32 bits of the integer register contents are used to fill the first of two longword entries in the VAX formatted argument list, while the high-order 32 bits are used to fill the second longword entry. This counts as two arguments in the VAX formatted argument list.
RASE$K_RA_I32 RASE$K_RA_U32 | The low-order 32 bits of the integer register contents are used to fill one longword entry in the VAX formatted argument list passed to the translated procedure. The high-order 32 bits are ignored. This counts as one argument in the VAX formatted argument list.
RASE$K_RA_FF | The single-precision contents of a floating-point register are used to fill one longword entry in the VAX formatted argument list passed to the translated procedure. This counts as one argument in the VAX formatted argument list. The Alpha store instruction STF is used to place the register contents into memory.
RASE$K_RA_FD RASE$K_RA_FG | The double-precision contents of a floating-point register are used to fill two longword entries in the VAX formatted argument list passed to the translated procedure. This counts as two arguments in the VAX formatted argument list. The Alpha store instruction STG is used to place the register contents into memory.
RASE$K_RA_FS RASE$K_RA_FT | Undefined.
PSIG$V_MEMORY_ARG_INFO Field Conversions
MASE$K_MA_Q MASE$K_MA_I32 | These convert like the RASE$K_RA_Q and RASE$K_RA_I32 field conversions, except that the Alpha argument list entry is stored in memory (rather in than a register).
PSIG$V_FUNC_RETURN Field Conversions
PSIG$K_FR_I64 | The translated code is returning a 64-bit result split between R0 and R1. The low-order 32 bits of R1 are shifted left and combined with the low-order 32 bits of R0 to form the 64-bit result that is returned to the native caller.
PSIG$K_FR_D64 | The translated code is returning a 64-bit result split between R0 and R1. Both R0 and R1 are sign extended from 32 to 64 bits and returned to the native caller in place.
PSIG$K_FR_I32 PSIG$K_FR_U32 | The translated code is returning a 32-bit result in R0. R0 is sign extended from 32 to 64 bits and returned to the native caller in place.
PSIG$K_FR_FF | The single-precision contents of the result in R0 is loaded into Alpha register F0.
PSIG$K_FR_FD PSIG$K_FR_FG | The double-precision contents in registers R0 and R1 are combined and loaded into Alpha register F0.
PSIG$K_FR_FS PSIG$K_FR_FT | Undefined.
PSIG$K_FR_FFC | The single-precision complex contents in registers R0 and R1 are loaded into Alpha registers F0 and F1.
PSIG$K_FR_FDC PSIG$K_FR_FGC | The translated code is returning a double-precision complex result using the hidden first parameter method (by reference). The storage for the result is allocated prior to the call and the address is passed as the extra parameter. Upon return, the result is copied from the temporary storage into the Alpha floating-point registers and returned to the native caller.
PSIG$K_FR_FSC PSIG$K_FR_FTC | Undefined.

In all 64-bit cases, the longword at the lower memory address forms the earlier argument in the VAX formatted argument list. Also, for single-precision floating-point types, the unused 32 bits of an Alpha 64-bit argument list entry are undefined.

#### 3.5.1.2 Translated-to-Native Code PSIG Conversions

The specific impact of the translated-to-native call conversions of the PSIG$V_REG_ARG_INFO and the PSIG$V_FUNC_RETURN field values are listed in Table 3-9.

Table 3-9 Translated-to-Native Conversion of the PSIG Field Values
Name | Impact
--- | ---
PSIG$V_REG_ARG_INFO Field Conversions
RASE$K_RA_Q | The contents of two successive longwords from the VAX formatted argument list are combined to form a single quadword value that is placed in an integer register. This counts as one argument in the Alpha argument list.
RASE$K_RA_I32 RASE$K_RA_U32 | The contents of one longword entry from the VAX formatted argument list is sign extended and placed in the integer register. This counts as one argument in the Alpha argument list.
RASE$K_RA_FF | A single longword entry from the VAX formatted argument list is used to form a floating-point value in a floating-point register. This counts as one argument in the Alpha argument list. The Alpha load instruction LDF is used to place the argument in the floating-point register.
RASE$K_RA_FD RASE$K_RA_FG | Two longword entries from the VAX formatted argument list are combined to form a single floating-point value in a floating-point register. This counts as one argument in the Alpha argument list. The Alpha load instruction LDG is used to place the argument in the floating-point register.
RASE$K_RA_FS RASE$K_RA_FT | Undefined.
PSIG$V_MEMORY_ARG_INFO Field Conversions
MASE$K_MA_Q MASE$K_MA_I32 | These convert like RASE$K_RA_Q and RASE$K_RA_I32 field conversions, except that the Alpha argument list entry is stored in memory (rather than a register). 1
PSIG$V_FUNC_RETURN Field Conversions
PSIG$K_FR_I64 | The native code is returning a 64-bit result in R0. The high 32 bits of R0 are moved to the low half of R1 and sign extended, and then R0 is sign extended from 32 to 64 bits. The 64-bit result is then returned to the translated caller in R0 and R1.
PSIG$K_FR_D64 | The native code is returning a 64-bit result split between R0 and R1. Both R0 and R1 are sign extended from 32 to 64 bits and returned to the translated caller in place.
PSIG$K_FR_I32 PSIG$K_FR_U32 | The native code is returning a 32-bit result in R0. R0 is sign extended from 32 to 64 bits and the result is then returned in place to the translated caller.
PSIG$K_FR_FF | The single-precision result in Alpha register F0 is stored in the low-order half of register R0. 1
PSIG$K_FR_FD PSIG$K_FR_FG | The double-precision result in Alpha register F0 is stored in the low-order halves of registers R0 and R1.
PSIG$K_FR_FS PSIG$K_FR_FT | Undefined.
PSIG$K_FR_FFC | The single-precision complex result in Alpha registers F0 and F1 is stored in the low-order halves of registers R0 and R1. 1
PSIG$K_FR_FDC PSIG$K_FR_FGC | The native code is returning a double-precision complex result in the Alpha floating-point registers. The result is copied into the storage given by the hidden first parameter passed by the translated caller.
PSIG$K_FR_FSC PSIG$K_FR_FTC | Undefined.

1Note that for single-precision floating-point types, the unused 32 bits of an Alpha 64-bit argument list entry are undefined.

Previous | Next | Contents | Index

| privacy and legal statement |
5973PRO_004.HTML