Document revision date: 30 March 2001

## VAX MACRO and Instruction Set Reference Manual

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#### 9.2.7.3 Instruction Descriptions

The following instructions are described in this section:

| Description and Opcode | Number of Instructions
--- | --- | ---
1. | Insert Entry into Queue at Head, Interlocked INSQHI entry.ab, header.aq | 1
2. | Insert Entry into Queue at Tail, Interlocked INSQTI entry.ab, header.aq | 1
3. | Insert Entry in Queue INSQUE entry.ab, pred.ab | 1
4. | Remove Entry from Queue at Head, Interlocked REMQHI header.aq, addr.wl | 1
5. | Remove Entry from Queue at Tail, Interlocked REMQTI header.aq, addr.wl | 1
6. | Remove Entry from Queue REMQUE entry.ab, addr.wl | 1

## INSQHI

> Insert Entry into Queue at Head, Interlocked

### Format

> opcode entry.ab, header.aq

### Condition Codes

| if {insertion succeeded} then
| begin
| N <--- 0;
| Z <--- (entry) EQL (entry+4); ! First entry in queue
| V <--- 0;
| C <--- 0;
| end;
| else
| begin
| N <--- 0;
| Z <--- 0;
| V <--- 0;
| C <--- 1; ! Secondary interlock failed
| end;

#### Exceptions

> reserved operand

### Opcodes

5C | INSQHI | Insert Entry into Queue at Head, Interlocked

### Description

> The entry specified by the entry operand is inserted into the queue following the header. If the entry inserted was the first one in the queue, the condition code Z-bit is set; otherwise it is cleared. The insertion is a noninterruptible operation. The insertion is interlocked to prevent concurrent interlocked insertions or removals at the head or tail of the same queue by another process even in a multiprocessor environment. Before performing any part of the operation, the processor validates that the entire operation can be completed. This method ensures that if a memory management exception occurs (see Appendix E), the queue is left in a consistent state. If the instruction fails to acquire the secondary interlock, then, if no exception conditions exist, the instruction sets condition codes and terminates.

Notes

1. Because the insertion is noninterruptible, processes running in kernel mode can share queues with interrupt service routines.
2. The INSQHI, INSQTI, REMQHI, and REMQTI instructions are implemented such that cooperating software processes in a multiprocessor may access a shared list without additional synchronization.
3. To set a software interlock realized with a queue, you can use the following:

       INSERT:
              INSQHI  ...             ; Was queue empty?
              BEQL    1$              ; Yes
              BCS     INSERT          ; Try inserting again
              CALL    WAIT(...)       ; No, wait

       1$:

4. During access validation, any access that cannot be completed results in a memory management exception even though the queue insertion is not started.
5. A reserved operand fault occurs if entry or header is an address that is not quadword aligned (that is, <2:0> NEQU 0) or if header<2:1> is not zero. A reserved operand fault also occurs if header equals entry. In this case, the queue is not altered.
6. If an interlocked queue instruction encounters both the secondary interlock set and an exception condition resulting from instruction execution, then it is UNPREDICTABLE whether the exception occurs or the instruction terminates after setting the condition codes.

## INSQTI

> Insert Entry into Queue at Tail, Interlocked

### Format

> opcode entry.ab, header.aq

### Condition Codes

| if {insertion succeeded} then
| begin
| N <--- 0;
| Z <--- (entry) EQL (entry+4); ! First entry in queue
| V <--- 0;
| C <--- 0;
| end;
| else
| begin
| N <--- 0;
| Z <--- 0;
| V <--- 0;
| C <--- 1; ! Secondary interlock failed
| end;

#### Exceptions

> reserved operand

### Opcodes

5D | INSQTI | Insert Entry into Queue at Tail, Interlocked

### Description

> The entry specified by the entry operand is inserted into the queue preceding the header. If the entry inserted was the first one in the queue, the condition code Z-bit is set; otherwise, it is cleared. The insertion is a noninterruptible operation. The insertion is interlocked to prevent concurrent interlocked insertions or removals at the head or tail of the same queue by another process even in a multiprocessor environment. Before performing any part of the operation, the processor validates that the entire operation can be completed. This method ensures that if a memory management exception occurs (see Appendix E), queue is left in a consistent state. If the instruction fails to acquire the secondary interlock, then, if no exception conditions exist, the instruction sets condition codes and terminates.

Notes

1. Because the insertion is noninterruptible, processes running in kernel mode can share queues with interrupt service routines.
2. The INSQHI, INSQTI, REMQHI, and REMQTI instructions are implemented such that cooperating software processes in a multiprocessor may access a shared list without additional synchronization.
3. To set a software interlock realized with a queue, you can use the following:

       INSERT:
              INSQHI  ...            ; Was queue empty?
              BEQL    1$             ; Yes
              BCS     INSERT         ; Try inserting again
              CALL    WAIT(...)      ; No, wait

       1$:

4. During access validation, any access that cannot be completed results in a memory management exception even though the queue insertion is not started.
5. A reserved operand fault occurs if entry, header, or (header+4) is an address that is not quadword aligned (that is, <2:0> NEQU 0) or if header<2:1> is not zero. A reserved operand fault also occurs if header equals entry. In this case, the queue is not altered.
6. If the instruction encounters both the secondary interlock set and an exception condition resulting from instruction execution, then it is UNPREDICTABLE whether the exception occurs or the instruction terminates after setting the condition codes.

## INSQUE

> Insert Entry in Queue

### Format

> opcode entry.ab, pred.ab

### Condition Codes

N||<--- (entry) LSS (entry+4); |
Z||<--- (entry) EQL (entry+4); ! First entry in queue |
V||<--- 0; |
C||<--- (entry) LSSU (entry+4); |

#### Exceptions

> None.

### Opcodes

0E | INSQUE | Insert Entry in Queue

### Description

> The entry specified by the entry operand is inserted into the queue following the entry specified by the predecessor operand. If the entry inserted was the first one in the queue, the condition code Z-bit is set; otherwise it is cleared. The insertion is a noninterruptible operation. Before performing any part of the operation, the processor validates that the entire operation can be completed. This method ensures that if a memory management exception occurs (see Appendix E), the queue is left in a consistent state.

Notes

1. The following three types of insertion can be performed by appropriate choice of the predecessor operand:
   - Insert at head:

         INSQUE  entry, h          ; h is queue head

   - Insert at tail:

         INSQUE  entry,@h+4        ; h is queue head
         (Note "@" in this case only)

   - Insert after arbitrary predecessor:

         INSQUE  entry,p           ; p is predecessor

2. Because the insertion is noninterruptible, processes running in kernel mode can share queues with interrupt service routines.
3. The INSQUE and REMQUE instructions are implemented such that cooperating software processes in a single processor may access a shared list without additional synchronization, if the insertions and removals are only at the head or tail of the queue.
4. To set a software interlock realized with a queue, you can use the following:

            INSQUE  ...             ; Was queue empty?
            BEQL    1$              ; Yes
            CALL    WAIT(...)       ; No, wait

       1$:

5. During access validation, any access that cannot be completed results in a memory management exception, even though the queue insertion is not started.

## REMQHI

> Remove Entry from Queue at Head, Interlocked

### Format

> opcode header.aq, addr.wl

### Condition Codes

| if {removal succeeded} then
| begin
| N <--- 0;
| Z <--- (header) EQL 0; ! Queue empty after removal
| V <--- {queue empty before this instruction};
| C <--- 0;
| end;
| else
| begin
| N <--- 0;
| Z <--- 0;
| V <--- 1; ! Did not remove anything
| C <--- 1; ! Secondary interlock failed
| end;

#### Exceptions

> reserved operand

### Opcodes

5E | REMQHI | Remove Entry from Queue at Head, Interlocked

### Description

> If the secondary interlock is clear, the queue entry following the header is removed from the queue and the address operand is replaced by the address of the entry removed. If the queue was empty prior to this instruction, or if the secondary interlock failed, the condition code V-bit is set; otherwise it is cleared.

> If the interlock succeeded and the queue is empty at the end of this instruction, the condition code Z-bit is set; otherwise, it is cleared. The removal is interlocked to prevent concurrent interlocked insertions or removals at the head or tail of the same queue by another process even in a multiprocessor environment. The removal is a noninterruptible operation. Before performing any part of the operation, the processor validates that the entire operation can be completed. This ensures that if a memory management exception occurs (see Appendix E), the queue is left in a consistent state. If the instruction fails to acquire the secondary interlock, then, if no exception conditions exist, the instruction sets condition codes and terminates.

Notes

1. Because the removal is noninterruptible, processes running in kernel mode can share queues with interrupt service routines.
2. The INSQHI, INSQTI, REMQHI, and REMQTI instructions are implemented so that cooperating software processes in a multiprocessor may access a shared list without additional synchronization.
3. To release a software interlock realized with a queue, you can use the following:

       1$:    REMQHI  ...             ; Removed last?
              BEQL    2$              ; Yes
              BCS     1$              ; Try removing again
              CALL    ACTIVATE(...)   ; Activate other waiters

       2$:

4. To remove entries until the queue is empty, you can use the following:

       1$:    REMQHI  ...             ; Anything removed?
              BVS     2$              ; No
                .
              process removed entry
                .
              BR      1$              ;
                .
       2$     BCS     1$              ; Try removing again
              queue empty

5. During access validation, any access that cannot be completed results in a memory management exception, even though the queue removal is not started.
6. A reserved operand fault occurs if header or (header + (header)) is an address that is not quadword aligned (that is, <2:0> NEQU 0) or if (header)<2:1> is not zero. A reserved operand fault also occurs if the header address operand equals the address of the addr operand. In this case, the queue is not altered.
7. If the instruction encounters both the secondary interlock set and an exception condition resulting from instruction execution, then it is UNPREDICTABLE whether the exception occurs or the instruction terminates after setting the condition codes.

## REMQTI

> Remove Entry from Queue at Tail, Interlocked

### Format

> opcode header.aq, addr.wl

### Condition Codes

| if {removal succeeded} then
| begin
| N <--- 0;
| Z <--- (header + 4) EQL 0; ! Queue empty after removal
| V <--- {queue empty before this instruction};
| C <--- 0;
| end;
| else
| begin
| N <--- 0;
| Z <--- 0;
| V <--- 1; ! Did not remove anything
| C <--- 1; ! Secondary interlock failed
| end;

#### Exceptions

> reserved operand

### Opcodes

5F | REMQTI | Remove Entry from Queue at Tail, Interlocked

### Description

> If the secondary interlock is clear, the queue entry preceding the header is removed from the queue and the address operand is replaced by the address of the entry removed. If the queue was empty prior to this instruction, or if the secondary interlock failed, the condition code V-bit is set; otherwise it is cleared.

> If the interlock succeeded and the queue is empty at the end of this instruction, the condition code Z-bit is set; otherwise it is cleared. The removal is interlocked to prevent concurrent interlocked insertions or removals at the head or tail of the same queue by another process, even in a multiprocessor environment. The removal is a noninterruptible operation. Before performing any part of the operation, the processor validates that the entire operation can be completed. This ensures that if a memory management exception occurs (see Appendix E), the queue is left in a consistent state. If the instruction fails to acquire the secondary interlock, then, if no exception conditions exist, the instruction sets condition codes and terminates.

Notes

1. Because the removal is noninterruptible, processes running in kernel mode can share queues with interrupt service routines.
2. The INSQHI, INSQTI, REMQHI, and REMQTI instructions are implemented to allow cooperating software processes in a multiprocessor system to access a shared list without additional synchronization.
3. To release a software interlock realized with a queue, you can use the following:

       1$:    REMQTI  ...             ; Removed last?
              BEQL    2$              ; Yes
              BCS     1$              ; Try removing again
              CALL    ACTIVATE(...)   ; Activate other waiters

       2$:

4. To remove entries until the queue is empty, you can use the following:

       1$:    REMQTI  ...             ; Anything removed?
              BVS     2$              ; No
                .
              process removed entry
                .
              BR      1$              ;
                .
       2$:    BCS     1$              ; Try removing again
              queue empty

5. During access validation, any access that cannot be completed results in a memory management exception, even though the queue removal is not started.
6. A reserved operand fault occurs if header, (header + 4), or (header + (header + 4)+4) is an address that is not quadword aligned (that is, <2:0> NEQU 0), or if (header)<2:1> is not zero. A reserved operand fault also occurs if the header address operand equals the address of the addr operand. In this case, the queue is not altered.
7. If the instruction encounters both the secondary interlock set and an exception condition resulting from instruction execution, then it is UNPREDICTABLE whether the exception occurs or the instruction terminates after setting the condition codes.

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