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501-1274



4/2xx CPU VME with FPC-6/4

 16.67MHz SF9010, Weitek 1164/1165, Sun-4 MMU with 16 hardware contexts.  VME
  bus interface.

 From left to right, with component side up and connector edge toward you
  (normal top edge at left), the rear edge of the board has: two serial ports
  (A and B from left to right (top/bottom)); an Ethernet connector; a switch to
  toggle between Normal and Diagnostic modes; eight LEDs (bit 0 to the
  right/bottom); a reset button; a keyboard connector; and a video connector.

 The video output is high-resolution ECL/TTL monochrome at 1600 x 1280, with
  89KHz horizontal sync and 66Hz vertical sync.

 There are a variety of jumper blocks, many of which (oddly) have separate
  designations for each pair of pins.  Locations below are given with component
  side up and connector edge toward you.

 J0301 (one pair in block in leftish center, by U2004 PROM)

  "External clock clock."                               UNJUMPED

 J0302 (one pair in block in leftish center, by U2004 PROM)

  46.153MHz clock enable.                               JUMPED

 J0303 (one pair in block in leftish center, by U2004 PROM)

  16MHz clock enable.                                   JUMPED

 J0304 (single jumper in leftish center, by U2003 PROM)

  VME clock enable.                                     JUMPED

 J0401 (block in far left)

  1-2   unused
  3-4   VME interrupt level 1                           JUMPED
  5-6   VME interrupt level 2                           JUMPED
  7-8   VME interrupt level 3                           JUMPED
  9-10  VME interrupt level 4                           JUMPED
  11-12 VME interrupt level 5                           JUMPED
  13-14 VME interrupt level 6                           JUMPED
  15-16 VME interrupt level 7                           JUMPED

 J2001 (farthest pair in block in far left, by U2001 PROM)

  Select 27512 PROMs.                                   JUMPED

 J2002 (middle pair in block in far left, by U2001 PROM)

  Select 27256 PROMs.                                   UNJUMPED

 J2003 (single jumper in near left)

  Connect 3V battery.                                   JUMPED

 J2201 (single jumper in near left, by battery)

  SCC (UART) clock enable.                              JUMPED

 J2401 (nearest pair in block in far left, by U2001 PROM)

  CPU is VME requester only                             UNJUMPED

 J2402 (rightmost pair in block in far center)

  CPU is arbiter/requester                              JUMPED

 J2403 (middle pair in block in far center)

  CPU is reset slave                                    UNJUMPED

 J2404 (leftmost pair in block in far center)

  CPU is reset master                                   JUMPED

 J2701 (single jumper in near middle, by LEDs)

  Debug jumper.                                         UNJUMPED

 J2801 (single jumper in far left)

  Enable system DVMA.                                   JUMPED

 J2902 (single jumper in leftish nearish middle)

  Jump for type-1 Ethernet transceiver, unjump for type-2.

 J2904 (location unknown, does not appear on diagram)

  "Null."                                               UNJUMPED

 Additional features of interest: the four boot PROMs form a line in the middle
  of the left half of the board, U2001-U2004 (1507-1504, farthest to nearest,
  respectively).  The IDPROM is near the U2004 PROM, at location U1901.  The 3V
  battery is along the near edge near serial port B.  The Ethernet fuse is in
  the near right, near the Weitek chips, at grid C29. The keyboard fuse is near
  the keyboard connector at grid A26.

 Note that 501-1274 boards must be 501-1274-12 or later to use a type-4
  keyboard.  Also, they must be 501-1274-13 or later to use a Xylogics 7053 SMD
  disk controller.

 The boot PROM version must be 1.7 or later to boot from an SMD disk connected
  to a Xylogics 7053 SMD disk controller.  Also, the boot PROM version must be
  3.0 or later when more than two 501-1576 16M memory boards are used.

 Power requirements are +5V @ 17.2A, -5V @ 1.3A, and +12V @ 0.4A.

  




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   Last modified: 2000.10.28.15.34.26 CDT
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